U00126 PERL - Practical Extraction and Report Language Version: 3.0, PL44, May 1991 Author: Larry Wall Operating System: ULTRIX V3.1, V4.0, ULTRIX/RISC V3.1, V4.X, UNIX System V Source Language: C Software Required: C Compiler Keywords: Language Interpreters Abstract: PERL is an interpreted language optimized for scanning arbitrary text files, extracting information from those text files, and printing reports based on that information. It's also a good language for many system management tasks. The language is intended to be practical (easy to use, efficient, complete) rather than beautiful (tiny, elegant, minimal). It combines some of the best features of C, SED, AWK, and SH, so people familiar with those languages should have little difficulty with it. (Language historians will also note some vestiges of CSH, PASCAL, and BASIC-PLUS.) Expression syntax corresponds quite closely to C expression syntax. Unlike most UNIX utilities, PERL does not arbitrarily limit the size of your data. If you've got the memory, PERL can take in your whole file as a single string. Recursion is of unlimited depth. The hash tables used by associative arrays grow as necessary to prevent degraded performance. PERL uses sophisticated pattern matching techniques to scan large amounts of data very quickly. Although optimized for scanning text, PERL can also deal with binary data, and can make DBM files look like associative arrays (where DBM is available). Setuid PERL scripts are safer than C programs through a dataflow tracing mechanism which prevents many stupid security holes. If you have a problem that would ordinarily use SED or AWK or SH, but it exceeds their capabilities or must run a little faster, and you don't want to write it in C, then PERL may be for you. There are also translators to turn your SED and AWK scripts into PERL scripts. Media (Service Charge Code): 600' Magnetic Tape (MA) Format: TAR \\ U00125 LangLAB Version: October 1990 Submitted by: Tanaka Hozumi, Tokyo Institute of Technology Operating System: SunOS V3.5, ULTRIX/RISC Source Language: Prolog Keywords: Language Interpreters, Utilities - ULTRIX/RISC Abstract: LangLAB is a software tool for the natural language analysis, which runs on several Prolog systems. User can obtain both the morphological analyzer and the parser by preparing grammars and dictionaries and translating them into Prolog programs with the LangLAB translators. Since the translators are written in YACC, a UNIX tool, LangLAB requires the UNIX environment. Notes: The Japanese language is not required for installation and execution of this program. However, there is a small amount of Japanese language in the HELP file. Media (Service Charge Code): User's Manual (EB), 600' Magnetic Tape (MA) Format: TAR \\ U00124 KCL-diffs for DECstations based on KCL Source, June 3, 1987 Version: March 1990 Submitted by: Arpita Datta, Wright State University, Research Center, Kettering, OH Operating System: ULTRIX - 32, ULTRIX/RISC Source Language: ASSEMBLY, C, LISP, RISC Software Required: KCL Source Code, Version: June 3, 1987 Hardware Required: DECstation 2100, DECstation 3100 Keywords: Utilities - ULTRIX/RISC Abstract: This software package contains the patches that modify the Kyoto Common Lisp (KCL) Source Code, Version: June 3, 1987, to make it run on the DECstation 2100 and DECstation 3100. Notes: The KCL Source Code, Version: June 3, 1987, can be purchased from the University of Texas, Computer Science Department. It is not available through DECUS. Documentation not available. Complete sources not included. Media (Service Charge Code): 600' Magnetic Tape (MA) Format: TAR, TK50 Tape Cartridge (TA) Format: TAR \\ U00122 POSE Version: February 1990 Submitted by: Charles E. Hammons, Martin Marietta Energy Systems, Inc., Oak Ridge, TN Operating System: MS-DOS V3.1, ULTRIX V1.0 through 4.X, VAX/VMS V4.X through 5.X, VENIX V2.0 Source Language: C Memory Required: 120KB-400KB Hardware Required: ANSI compatible terminal Keywords: Editors, Word Processing, Utilities - ULTRIX/UNIX Abstract: POSE (Portable Screen Editor) is a dual-function program written in the C language that combines the capabilities of a text editor and those of a text formatter such as would be provided by a word processor or typesetter. POSE has been developed with portability as a primary goal so the code can be easily transported among systems. POSE has been written to follow the IEEE P1003.1 Standard, POSIX, so it can run on any compliant system. POSE was written to run under the following operating systems: any POSIX compliant operating system, Digital Equipment Corporation's ULTRIX and VMS, Bell Laboratory's UNIX System V, and University of California/Berkeley's UNIX 4.3 BSD, and PC DOS. This includes CRAY/UNICOS currently without full screen mode support. POSE offers an extended set of search, edit, print, and iteration commands. POSE can also be used for input and editing using full screen mode on an ANSI compatible terminal. POSE allows the user to view the final results of a formatted document on the screen as well as formatting directly to the printer. The POSE formatter is similar to Digital Equipment Corporation's RUNOFF program and the NROFF program which runs in the UNIX environment. The formatter features easily generated scientific equations and output streams. It supports ANSI page image devices such as the LN03 and the Talaris/Richo units, ANSI compatible CRTs, most (ASCII) hardcopy terminals, and some older non-standard print devices. Notes: This version is distributed in TAR format for use on ULTRIX/UNIX systems. For a description of the VAX/VMS version, see DECUS No. V00469. Media (Service Charge Code): 600' Magnetic Tape (MA) Format: TAR \\ U00121 EDIF 200 Version: 6, May 1989 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Software Required: C Compiler Keywords: Utilities - ULTRIX/UNIX Abstract: The Berkeley EDIF 200 software is an environment for managing EDIF 200. The project implements a translator- building toolkit that provides all facilities necessary for building a translator to or from EDIF. Using the toolkit, it is possible to construct any translator; the translator-writer should only have to provide access to the source or target data format. The Berkeley EDIF software consists of an efficient in-core data-structure specifically designed to manipulate EDIF. Surrounding this data-structure are various support routines for reading, writing, expanding MACROS, evaluating expressions, and executing statements. The goal of the Berkeley EDIF software is to provide an environment that will support the manipulation of EDIF in a straightforward manner as well as an environment that will provide an easy path for the construction of translators to and from EDIF. The ordering information for the manuals is as follows: . Order U00121 (EC) for "EDIF USER'S GUIDE" . Order U00121 (EE) for "The BERKELEY EDIF Software EDIF Library Manual Pages" Release notes are distributed with each order. Notes: Operating system ULTRIX V2.2, V2.4, V3.0, or UNIX V4.2, V4.3BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EC), User's Manual (EE), 2400' Magnetic Tape (PA) Format: TAR \\ U00120 ELOGIC Version: May 1989 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Software Required: VAX C Compiler Keywords: Circuit Simulation, Utilities - ULTRIX/UNIX Abstract: The ELOGIC tape consists of a timing verifier (E-TV) based on the ELOGIC delay model. E-TV is designed for the switch- level timing verification of MOS digital circuits. It reports the possiblity of timing errors. It provides tradeoffs between efficiency and precision, both within an analysis and across analyses. It finds and reports the worst delay paths in combinational circuits. For synchronous systems, E-TV computes clock skew, then uses the clock skew for detecting timing errors and listing logic paths between pairs of clocked storage elements in order of worst evaluation-time margin. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Operating System UNIX V4.2 or V4.3 BSD is required. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (ED), 600' Magnetic Tape (MA) Format: TAR \\ U00118 PROUD Version: 1.0, February 1989 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 3MB Software Required: VAX C Compiler Keywords: Utilities - ULTRIX/UNIX Abstract: PROUD is an automatic, efficient circuit placement package designed for high complexity row-structured sea-of-gates, gate array, and standard cell designs. Its most important capability is that it can handle complex design in a short time with excellent results. A typical high complexity circuit with one million transistors can be placed within three hours on a VAX 8650 (a six MIPs machine) with excellent results. PROUD has two phases: constructive phase and iterative improvement phase. In constructive phase, PROUD employs Successive Over-Relaxation method to solve repeatedly sparse linear equations and hierarchically partitions the modules to final legal locations. An effective Block Gauss-Seidel scheme is also devised to achieve global optimum results in this phase. In iterative improvement phase, local perturbations such as module rotation, I/O pad position adjustment, module swap or insertion are performed to further improve the quality of placement results. It is easy to use the package by providing four files that describe cell structure, net list, control parameter, chip configuration and net weighting. User can specify different row lengths in the control file. This feature is purposely made for allocating routing space. For a description of the VAX/VMS version of PROUD, see DECUS No. V00397. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Operating System UNIX V4.2, V4.3 BSD is required. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), 600' Magnetic Tape (MA) Format: TAR \\ U00117 SuperCrystal Version: February 1989 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 3MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: SuperCrystal is a circuit simulator suitable for large MOS VLSI circuits. It makes various restrictions on the types of circuits it accepts, and capitalizes on commonly found features of digital circuits to provide approximate voltage waveforms at nodes in the circuit with reasonable speed. Empirical evidence indicates that the voltage waveforms predicted by SuperCrystal are reasonably close to waveforms determined by the circuit simulation program SPICE. In addition, SuperCrystal is significantly faster than SPICE. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EC), 600' Magnetic Tape (MA) Format: TAR \\ U00116 Spectre Version: 1a1, February 1989 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 3MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: Spectre is a frequency domain based nonlinear circuit simulator. It is able to find the large-signal steady-state response of a nonautonomous nonlinear circuit. When used on circuits behaving only mildly nonlinearly with few harmonics present, Spectre can be significantly more efficient and accurate than traditional time domain simulators. This is particularly true if the circuit is high-Q, narrow-band, has slowly responding bias networks, or contains distributed components. Besides finding the large-signal periodic and quasiperiodic steady-state response of a circuit, Spectre is also able to find its DC operating point and perform a small signal analysis; calculating voltages, currents, and S-parameters. Because Spectre operates exclusively in the frequency domain, it is able to use much more accurate and flexible distributed device models (including such effect as loss and dispersion) than traditional time domain simulators. It is also able to read and write S-parameter data files. Spectre currently supports resistors, capacitors, inductors, transformers, voltage sources, current sources, ports, voltage controlled voltage sources, voltage controlled current sources, transmission lines (lossless and lossy), microstrip lines, linear N-ports that take their characteristics from S-parameter data files, diodes, BJTs, JFETs, GaAsFETs, and polynomial voltage controlled current sources. Spectre is a simulation engine only. It outputs its results into a rawfile for use with Nutmeg. The rawfile is not meant to be readable by the user. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EC), 600' Magnetic Tape (MA) Format: TAR \\ U00115 Sparse Version: 1.3, June 1988 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: UNIX Source Language: C Memory Required: 1.5MB Software Required: C Compiler Keywords: Circuit Simulation, Mathematical, Utilities - ULTRIX/UNIX Abstract: Sparse is a flexible package of subroutines written in C used to quickly and accurately solve large sparse systems of linear equations. The package is able to handle arbitrary real and complex square matrix equations. Besides being able to solve linear systems, it is also able to quickly solve transposed systems, find determinants, and estimate errors due to ill-conditioning in the system of equations and instability in the computations. It also provides a test program that is able to read matrix equations from a file, solve them, and print useful information about the equation and its solution. Sparse is generally as fast or faster than other popular sparse matrix packages when solving many matrices of similar structure. Sparse does not require or assume symmetry and is able to perform numerical pivoting to avoid unnecessary error in the solution. It handles its own memory allocation, which allows the user to forgo the hassle of providing adequate memory. It also has a natural, flexible, and efficient interface to the calling program. Sparse was originally written for use in circuit simulators and is particularly apt at handling node and modified-node admittance matrices. The systems of linear generated in a circuit simulator stem from solving large systems of nonlinear equations using Newton's method and integrating large stiff systems of ordinary differential equations. However, Sparse is also suitable for other uses, one in particular is solving the very large systems of linear equations resulting from the numerical solution of partial differential equations. Release notes are distributed with each order. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EB), 600' Magnetic Tape (MA) Format: TAR \\ U00114 ADORE Version: 2.1, September 1988 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 1.5MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: ADORE is a module generator for switched-capacitor (SC) filters which can be adapted to a variety of process technologies. It can generate layouts for SC circuits comprising ratioed capacitors, double-throw switches, and operational amplifiers (op amps). ADORE uses a fixed floor plan, and employs several algorithms to generate compact layouts for SC filters with small amounts of interconnect parasitics. ADORE accepts any library information it requires from an OCT database format. The generated layouts are also stored in OCT. The conversion from OCT to CIF and visa versa can be easily done with the help of OCTTOCIF and CIFTOOCT programs. The ordering information for the manuals is as follows: . Order U00114 (EA) for "Layout Generator User's Guide" . Order U00114 (EC) for "Automatic Synthesis and Layout User's Manual" Notes: Operating system UNIX V4.2 or V4.3 BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), User's Manual (EC), 600' Magnetic Tape (MA) Format: TAR \\ U00113 Creep Version: 1.5, May 1988 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX V4.3BSD, UNIX V4.2 Source Language: C Memory Required: 1.5MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: CREEP is a two-dimensional (2D) process simulator designed to solve certain creep-flow problems encountered in integrated circuit fabrication technology. Its most important capability is the prediction of general 2D silicon oxidation, using stress-dependent oxidation models. It also performs glass-reflow or film-shrinkage simulation as subset-problems of silicon oxidation. CREEP is equipped with a flexible and robust data structure for handling geometric information. All geometric structures are represented using nodes and segments; hence, fairly general geometric structures can be handled by the CREEP program. A finite-element mesh generator has also been built into CREEP. Mesh generation is done automatically at every time-step of the computation, with the user supplying only a mesh-density parameter. Ordering information for the documentation is as follows: . Order DECUS No. U00113 (EB) for the "CREEP - A 2D Creep-Flow Process Simulator" User's Guide. . Order DECUS No. U00113 (ED) for the "Finite-Element Methods for Process Simulation Application to Silicon Oxidation" Manual. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EB), User's Manual (ED), 600' Magnetic Tape (MA) Format: TAR \\ U00112 SPLICE3 Version: 3.0, March 1988 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 1.5MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: SPLICE3 is a circuit simulation program for large-scale integrated circuits. It performs electrical simulation using event-driven selective-trace techniques. This analysis is done using the Iterated Timing Analysis (ITA) algorithm, which performs an accurate electrical waveform analysis up to fifty times faster than SPICE2. Release notes are distributed with each order. Notes: Operating system UNIX V4.2 or V4.3BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. For a description of the VAX tape, see DECUS No. V00091. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EE), 600' Magnetic Tape (MA) Format: TAR \\ U00111 PLAtools Version: November 1987 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C, RATFOR Memory Required: 1.5MB Software Required: C Compiler, RATFOR Compiler Keywords: Utilities - ULTRIX/UNIX Abstract: The Berkeley PLA Tools are a set of tools designed for performing logical and topological optimization as well as test pattern generation of programmable logic arrays (PLAs). The tools form a system encompassing the design of PLAs from the specification of algebraic equations, through logic minimization and folding, to final physical layout and test pattern generation. These tools also support the optimization of finite-state machines (FSMs) when the machine is implemented as a programmable logic array. Notes: Operating system UNIX V4.1, V4.2, or V4.3BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. For a description of the VAX tape, see DECUS No. V00174. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EE), 600' Magnetic Tape (MA) Format: TAR \\ U00109 SPICE2 Version: 2G.6, March 1988 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C, FORTRAN 77 Memory Required: 1.5MB Software Required: C Compiler, FORTRAN 77 Compiler Keywords: Circuit Simulation Abstract: SPICE2 is a general-purpose circuit simulation program for nonlinear DC, nonlinear transient, and linear AC analysis. Circuits may contain resistors, capacitors, inductors, mutual inductors, ideal switches, independent voltage and current sources, four types of dependent sources, transmission lines and the five most common semiconductor devices: diodes, BJTs, JFETs, GaAs MESFETSs, and MOSFETS. Release notes are distributed with each order. Notes: Operating system UNIX V4.1BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. For a description of the VAX tape, see DECUS No. V00216. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), 600' Magnetic Tape (MA) Format: TAR \\ U00108 GLITTER2 Version: 2, January 1987 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 964W Software Required: C Compiler Keywords: Circuit Simulation Abstract: GLITTER2 is a two-layer channel routing and compaction tool for the layout design of integrated circuits. It consists of the gridless channel router GLITTER and a newly-developed channel spacer NUTCRACKER. The gridless approach we use can take advantage of different design rules on the two routing layers. No columns or tracks will be generated; only the wire width, spacing and contact size are considered. The major feature of this tool is to route channels with different wire widths and arbitrary terminal positions. It is also capable of handling channels with irregular boundaries. To minimize the channel height, contacts will be slid and necessary jogs will be automatically inserted. For channels with cyclic constraints, a preprocessor is used to generate the doglegs. The routing algorithm starts with a cycle-free weighted constraint graph, and generates a solution which minimizes the channel height. Notes: Operating system UNIX V4.3BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), 600' Magnetic Tape (MA) Format: TAR \\ U00107 MAHJONG Version: 1, October 1986 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 789W Software Required: C Compiler Keywords: Circuit Simulation Abstract: MAHJONG is a user-configurable test pattern generation (TPG) system for combinational logic circuits. It takes as input a circuit file and performs a tailored TPG process specified by the user through various options. MAHJONG contains two front-ends, a deterministic TPG program, several heuristics for guided TPG, and a back-end. A parallel fault simulator is embedded in the deterministic TPG program as well as in the back-end and is not directly accessible to the users. The front-ends are heuristic TPG programs designed to efficiently generate test vectors for easily detectable faults. Users have the choice of the VICTOR-III front-end, the random front-end, or no front-end at all. Hard-to-detect faults are handled by the deterministic TPG program. Currently, this program is based on the PODEM algorithm. The back-end is a test compactor based on fault simulation and is very cost-effective. Four guided TPG heuristics are currently provided for the PODEM-based deterministic program. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley . Documentation may or may not be on magnetic media. Media (Service Charge Code): 600' Magnetic Tape (MA) Format: TAR \\ U00106 RELAX2.3 Version: 2.3, March 1988 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 10MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: RELAX2.3 performs a fast and accurate transient analysis of Metal-Oxide-Semiconductor (MOS) integrated circuits. The program uses a mixture of direct methods, like those used in the SPICE2 program, DECUS Program No. U00109, and a modified version of the Waveform Relaxation (WR) algorithm. This combination of methods can greatly improve the computational efficiency of circuit simulation for MOS digital circuits by exploiting their loose coupling and relative inactivity, and can still efficiently solve tightly coupled analog circuits by switching automatically to direct methods when appropriate. Using this combination of methods, RELAX2.3 can produce results of the same accuracy as SPICE2 for both analog and digital MOS integrated circuits, but often uses less than ten percent of the computer time. The ordering information for the manuals is as follows: . Order U00106 (EA) for the "RELAX2.3 User's Guide" . Order U00106 (ED) for the "MULTIRATE INTEGRATION User's Manual" Release notes are distributed with each order. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. For a description of the VAX tape, see DECUS No. V00141. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), User's Manual (ED), 600' Magnetic Tape (MA) Format: TAR \\ U00105 SPICE3 Version: 3B.1, April 1987 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Memory Required: 65MB Software Required: C Compiler Keywords: Circuit Simulation Abstract: SPICE is a general-purpose circuit simulation program for nonlinear DC, nonlinear transient, and linear AC analysis. Circuits may contain resistors, capacitors, inductors, mutual inductors, ideal switches, independent voltage and current sources, four types of dependent sources, transmission lines and the five most common semiconductor devices: diodes, BJTs, JFETs, GaAs MESFETSs, and MOSFETS. The ordering information for the manuals is as follows: . Order U00105 (EA) for the "User's Guide" . Order U00105 (EB) for the "User's Manual" . Order U00105 (EC) for the "Programmer's Manual" Release notes are distributed with each order. Notes: Operating system UNIX V4.2 and V4.3BSD is required. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. For a description of the VAX tape, see DECUS No. V00006. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), User's Manual (EB), User's Manual (EC), 600' Magnetic Tape (MA) Format: TAR \\ U00104 Wombat Version: October 1983 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX, UNIX V4.3BSD, VAX/VMS V4.2 Source Language: C Memory Required: 215KB Software Required: C Compiler Keywords: Utilities - ULTRIX/UNIX Abstract: Currently, most integrated circuit layouts are hand checked to determine their correctness. This manual procedure is very time-consuming and does not guarantee an error-free circuit. The WOMBAT program has been developed to overcome this problem. WOMBAT compares two netlists. One is usually based on the simulator input and the other is often extracted from the layout. However, such is not necessarily the case and WOMBAT makes no assumptions about the number of pins or the technology of the circuit elements in the schematics. One can specify how the pins of individual elements permute as well as an initial correspondence between circuit elements and nets. WOMBAT generates a list of corresponding elements and nets and notes any differences. Release notes are distributed with each order. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California- Berkeley. Program is distributed on a TAR formatted tape. For a description of the VAX tape, see DECUS No. V00092. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EC), 600' Magnetic Tape (MA) Format: TAR \\ U00103 Mighty Version: 1.6, October 1986 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: UNIX/ULTRIX, VAX/VMS Source Language: C Memory Required: 720KB Software Required: C Compiler Keywords: Utilities - ULTRIX/UNIX Abstract: MIGHTY is a two layer detailed router for general routing problems, including switchboxes, channels, and partially routed areas. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear chain, the pins can be on the boundaries of the region or inside it, and obstructions can be of any shape and form. Notes: Program is distributed on a TAR formatted tape. This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): 600' Magnetic Tape (MA) Format: TAR \\ U00102 KIC2 Version: 2, October 1983 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Software Required: C Compiler Keywords: Artwork Editor, Graphics, Utilities - ULTRIX/UNIX Abstract: KIC2 is an interactive, two-dimensional, color graphics editor intended primarily for the mask level design of integrated circuits. KIC2 has been designed as a powerful, inexpensive, user-friendly graphics editor that will run on most low to medium performance graphics terminals. Data that is generated by KIC2 can be represented by an intermediate graphic description language, such as CIF (Caltech Intermediate Form) or Calma STREAM, which permits the data to be easily transported to other layout systems. Also, the geometric database used by KIC2 can be used to interface to other tools, such as a layout rules checking program. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley . For a description of the VAX tape see DECUS No. V00044. Restrictions: U.S. Government export regulations prohibit the distribution of this program outside of the United States without the appropriate export license. UNIX V4.2, V4.3 or ULTRIX V1.1 is required. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (ED), 600' Magnetic Tape (MA) Format: TAR \\ U00101 Timberwolf Version: 3.2, March 1986 Submitted by: University of California at Berkeley, through Digital Equipment Corp Operating System: ULTRIX/UNIX Source Language: C Software Required: C Compiler Keywords: Utilities - ULTRIX/UNIX Abstract: Timberwolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing have been developed. Experimental results on industrial circuits show that area savings over existing layout programs ranging from 15 to 62 percent are possible. Notes: This program was developed by the Computer-Aided Design Group, Department of Electrical Engineering and Computer Sciences, University of California- Berkeley. Documentation may or may not be on magnetic media. Media (Service Charge Code): User's Manual (EA), 600' Magnetic Tape (MA) Format: TAR \\