.!INSTR.RNO - Concise description of the VAX instruction set .! .! RUNOFF operation instructions: .! This file can either produce a printed document or an entry .! for VMS online HELP. Use the command .! .! $ RUNOFF/NOBOLD/NOUNDER/OUT=INSTR.HLP INSTR.RNO .! .! to create the online help entry. INSTR.HLP can be inserted .! into any VMS help library. Use the command .! .! $ RUNOFF/OUT=INSTR.MEM/VAR=MANUAL INSTR.RNO .! .! To create a document for printing. .! .if manual .! .! We set the layout so that running page numbers are on the bottom .! .lo 1,2 .st .! .! Initial right margin - sections should never set it higher than this. .! Set page size too. .ps 60,70 .rm 70 .! .! Header level setup .sthl 6,0,0,8,9,1,1,9,2 .dhl D,D,lu,d,ll,ll .! .! .c; .sk 2 .c;THE VAX INSTRUCTION SET .title VAX INSTRUCTION SET .sk 2 .c;Ned Freed, 18-Jan-1985 .c;MATHLIB Project .c;Harvey Mudd College .sk 3 .else manual .NO NUMBER .NO PAGING .STHL 5,1,1 .endif manual .! .ifnot manual 1 Instruction_Set .br This help file describes the formats and types of available VAX-11 machine instructions. To use this help facility, just specify the specific instruction to be described as a subtopic. .s 1 These descriptions are adapted from the VAX-11 Architecture Handbook, with the addition of some extra tables. All instruction timing measurements were done either by Oregon Software or by Digital. .else manual .save .flags bold .hl 1 ^*Overview\* .restore This document describes the instruction set of the VAX-11 computer. These descriptions are useful both to the assembly language programmer and to the high-level language programmer who wishes to examine the machine code produced for his or her program. All the VAX/VMS compilers will optionally list the generated machine instructions. .s 1 These descriptions are adapted from the ^&VAX-11 Architecture Handbook\&. This document is more concise and is better organized (alphabetically by instruction) than the original handbook. In addition some new tables are included. .endif manual .s 1 At the present time the instructions EDITPC, INSQHI [780-12.80], .index ^Instructions, machine>^Operand>^Source mode S_^_#literal . . .[0.00] (Rn) . . . . . .[0.40] -(Rn) . . . . .[0.40] (Rn)+ . . . . .[0.40] @(Rn)+ . . . . .[1.00] B_^D(Rn) . . . .[0.40] W_^D(Rn) . . . .[0.40] L_^D(Rn) . . . .[0.80] @B_^D(Rn) . . . .[1.00] @W_^D(Rn) . . . .[1.00] @L_^D(Rn) . . . .[1.40] _#literal . . . .[0.80] @_#address . . .[0.80] (Rn)[Rn] . . . .[1.00] -(Rn)[Rn] . . .[1.00] (Rn)+[Rn] . . .[1.00] @(Rn)+[Rn] . . .[1.40] B_^D(Rn)[Rn] . .[1.00] W_^D(Rn)[Rn] . .[1.00] L_^D(Rn)[Rn] . .[0.80] @B_^D(Rn)[Rn] . .[1.40] @W_^D(Rn)[Rn] . .[1.40] @L_^D(Rn)[Rn] . .[1.40] @_#address[Rn] .[1.00] .s 1 .test page 11 Destination mode times for a 780 with or without FPA: .s 1 .index ^Instructions, machine>^Operand>^Destination mode (Rn) . . . . . .[0.40] -(Rn) . . . . .[0.40] (Rn)+ . . . . .[0.60] @(Rn)+ . . . . .[1.00] B_^D(Rn) . . . .[0.40] W_^D(Rn) . . . .[0.60] L_^D(Rn) . . . .[0.60] @B_^D(Rn) . . . .[1.00] @W_^D(Rn) . . . .[1.20] @L_^D(Rn) . . . .[1.20] @_#address . . .[0.60] (Rn)[Rn] . . . .[1.00] -(Rn)[Rn] . . .[1.00] (Rn)+[Rn] . . .[1.00] @(Rn)+[Rn] . . .[1.40] B_^D(Rn)[Rn] . .[1.00] W_^D(Rn)[Rn] . .[1.00] L_^D(Rn)[Rn] . .[0.60] @B_^D(Rn)[Rn] . .[1.40] @W_^D(Rn)[Rn] . .[1.40] @L_^D(Rn)[Rn] . .[1.40] @_#address[Rn] .[1.00] .s 1 .test page 6 Source mode times for a 750 with or without FPA: .s 1 .index ^Instructions, machine>^Operand>^Source mode (Rn) . . . . . .[0.20] B_^D(Rn) . . . .[0.40] B_^W(Rn) . . . .[0.70] (RN)[Rn] . . . .[0.90] .s 1 .test page 6 Destination mode times for a 750 with or without FPA: .s 1 .index ^Instructions, machine>^Operand>^Destination mode (Rn) . . . . . .[0.70] .s 1 .test page 6 Source mode times for a 730 with or without FPA: .s 1 .index ^Instructions, machine>^Operand>^Source mode (Rn) . . . . . .[0.70] B_^D(Rn) . . . .[1.20] B_^W(Rn) . . . .[3.00] (RN)[Rn] . . . .[2.63] .s 1 .test page 6 Destination mode times for a 730 with or without FPA: .s 1 .index ^Instructions, machine>^Operand>^Destination mode (Rn) . . . . . .[1.70] .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*ACB instructions\* .restore .send toc .endif global .index ^Instructions, machine>* (10**(-cnt-1))}} * (10**cnt); .if manual .s 1 .endif manual C. Codes: N = {{dst string} LSS 0}, Z = {{dst string} EQL 0}, V = {decimal overflow}, C = 0 .if manual .s 1 .endif manual Exceptions: Reserved operand, decimal overflow .if manual .s 1 .endif manual Opcodes: F8 ASHP Arithmetic shift packed .if manual .s 1 .endif manual Description: src as specified by srclen and srcaddr is scaled by a power of 10 specified by cnt. dst is replaced by the result. A positive cnt effectively multiplies, a negative cnt effectively divides and a zero cnt just moves src to dst while affecting the condition codes. If cnt is negative the result is rounded using round. .if manual .s 1 .endif manual Notes: After execution R0 = 0, R1 = address of the byte of the most significant digit of src, R2 = 0, R3 = address of the most significant digit of dst. All condition codes and R0-R3 are unpredictable if src overlaps dst, src contains an invalid nibble, or a reserved operand exception occurs. When cnt is negative the result is rounded by adding bits 3:0 of round to the most significant low order digit discarded and propogating any carry through to higher order digits of dst. If bits 7:4 of round are nonzero or if 3:0 contain an illegal packed decimal digit the result is unpredictable. round should normally be 5, or 0 if truncation is desired. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*Bxxx instructions\* .restore .send toc .endif global .else manual 2 Bxxx .endif manual .nf Purpose: branch - test condition code(s) .if manual .s 1 .endif manual Format: opcode displ.bb .if manual .s 1 .endif manual Operation: if {condition} then PC = {PC + SEXT (displ)} .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: None .if manual .s 1 .endif manual Opcodes: 12 {Z EQL 0} BNEQ Branch not equal (s) .index ^Instructions, machine>}; Z = Z AND {NOT mask_<2_>} V = V AND {NOT mask_<1_>}; C = C AND {NOT mask_<0_>} .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcode: B8 BICPSW Bit clear PSW [780-1.00] .if manual .s 1 .endif manual Description: The PSW is ANDed with the complement of mask and PSW is replaced by the result. .if manual .s 1 .endif manual Notes: A reserved operand fault occurs if mask_<15:8_> is not zero. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*BISxx instructions\* .restore .send toc .endif global .else manual 2 BISxx .endif manual .nf Purpose: bit set - perform logical inclusive OR of two integers .if manual .s 1 .endif manual Format: opcode mask.rx,dst.mx ;2 operand opcode mask.rx,src.rx,dst.rx ;3 operand .if manual .s 1 .endif manual Operation: dst = dst OR mask ;2 operand dst = src OR mask ;3 operand .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C .if manual .s 1 .endif manual Exceptions: None .if manual .s 1 .endif manual Opcodes: 88 BISB2 Bit set byte, 2 operand [780-0.40] .index ^Instructions, machine>; Z = Z OR mask_<2_> V = V OR mask_<1_>; C = C OR mask_<0_> .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcode: B8 BISPSW Bit set PSW [780-1.00] .if manual .s 1 .endif manual Description: The PSW is ORed with mask and PSW is replaced by the result. .if manual .s 1 .endif manual Notes: A reserved operand fault occurs if mask_<15:8_> is not zero. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*BITx instructions\* .restore .send toc .endif global .else manual 2 BITx .endif manual .nf Purpose: test a set of bits for all zero .if manual .s 1 .endif manual Format: opcode mask.rx,src.rx .if manual .s 1 .endif manual Operation: tmp = {src AND mask} .if manual .s 1 .endif manual C. Codes: N = {tmp LSS 0}, Z = {tmp EQL 0}, V = 0, C = C .if manual .s 1 .endif manual Exceptions: None .if manual .s 1 .endif manual Opcodes: 93 BITB Bit test byte [780-0.40] .index ^Instructions, machine> EQL teststate then PC = {PC + SEXT (displ)} .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: None .if manual .s 1 .endif manual Opcodes: E8 BLBS Branch on low bit set [780-1.00] .index ^Instructions, machine> = 0; {breakpoint fault} .if manual .s 1 .endif manual C. Codes: N = 0, Z = 0, V = 0, C = 0 .if manual .s 1 .endif manual Exceptions: None .if manual .s 1 .endif manual Opcode: 03 BPT Breakpoint fault .if manual .s 1 .endif manual Description: This instruction is used, together with the T-bit, to implement debugging facilities. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*BR instructions\* .restore .send toc .endif global .index ^Instructions, machine>
); {maximize privilege}; tmp3 = SEXT(code); if {PSL_ EQLU 1} then HALT; PSL___SP = SP tmp4 = tmp2__sp; PROBEW (from tmp4 - 1 to tmp4 - 12 with mode = tmp2); if {access violation} then {initiate access violation fault}; if {translation not valid} then {initiate translation not valid}; {initiate CHMx exception with new__mode = tmp2 and parameter = tmp3 using 40 + tmp1*4 as SCB offset using tmp4 as the new SP and not storing SP again} .if manual .s 1 .endif manual C. Codes: N = 0, Z = 0, V = 0, C = 0 .if manual .s 1 .endif manual Exceptions: Halt .if manual .s 1 .endif manual Opcodes: BC CHMK Change mode to kernel .index ^Instructions, machine> = {coefficient of x**(order-1-n)}. This operation is done automatically by the system library routine LIB_$CRC__TABLE (poly.rl, table.ab). The table is the location of a 64-byte table into which the result will be written. This instruction will produce an unpredictable result if the table is not well formed. All well formed tables have entry[0] = 0 and entry[8] = a polynomial created by the relationship given above. If the data is of zero length, R0 = inicrc. The times shown assume a 16 byte CRC operation. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*CVTxx instructions\* .restore .send toc .endif global .else manual 2 CVTxx .endif manual .index ^Instructions, machine>. After execution R0 = R2 = 0, R1 = address of the sign byte of src and R3 = address of the most significant digit of dst. dst and R0-R3 are unpredictable if src overlaps dst or a reserved operand abort occurs. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*CVTTP instruction\* .restore .send toc .endif global .index ^Instructions, machine>), or if the translation of the least significant digit produces an invalid decimal digit or sign nibble. If src is -0, dst will be set to +0 with N = 0 and Z = 1. If srclen is 0 dst will be set to +0 and tbl will not be referenced. The times shown above assume 7 digits are packed; if 18 are packed the times are: [780-25.57, 750-36.27, 730-87.51] [780F-25.57, 750F-36.27, 730F-86.55] .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*DECx instructions\* .restore .send toc .endif global .else manual 2 DECx .endif manual .nf Purpose: decrement - subtract 1 from an integer .if manual .s 1 .endif manual Format: opcode dif.mx .if manual .s 1 .endif manual Operation: dif = dif - 1 .if manual .s 1 .endif manual C. Codes: N = dif LSS 0, Z = dif EQL 0 V = {integer overflow}, C = {borrow from MSB} .if manual .s 1 .endif manual Exceptions: Integer overflow .if manual .s 1 .endif manual Opcodes: 97 DECB Decrement byte [780-0.40] .index ^Instructions, machine> NEQU kernel then {reserved to Digital opcode fault} else {halt the processor} .if manual .s 1 .endif manual C. Codes: N = 0, Z = 0, V = 0, C = 0 (fault) Unaffected (processor halt) .if manual .s 1 .endif manual Exceptions: Reserved to Digital opcode .if manual .s 1 .endif manual Opcode: 00 HALT Halt .if manual .s 1 .endif manual Description: If process is running in kernel mode, the processor is halted. Otherwise, an opcode reserved to Digital fault occurs. This opcode is 0 to trap many branches to data. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*INCx instructions\* .restore .send toc .endif global .else manual 2 INCx .endif manual .nf Purpose: increment - add 1 to an integer .if manual .s 1 .endif manual Format: opcode sum.mx .if manual .s 1 .endif manual Operation: sum = sum + 1 .if manual .s 1 .endif manual C. Codes: N = {sum LSS 0}, Z = {sum EQL 0}, V = {integer overflow}, C = {carry from MSB} .if manual .s 1 .endif manual Exceptions: Integer overflow .if manual .s 1 .endif manual Opcodes: 96 INCB Increment byte [780-0.40] .index ^Instructions, machine> .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcode: F0 INSV Insert field [780-3.40] [780-3.51, 750-4.10, 730-14.83] [780F-3.41, 750F-4.10, 730F-14.63] .if manual .s 1 .endif manual Description: The field specified by pos, size and base is replaced by bits {size-1}:0 of src. If size is 0 no action occurs. .if manual .s 1 .endif manual Notes: A reserved operand fault occurs if size GTRU 32 or pos GTRU 31, size NEQU 0 and the field is contained in the registers. On such a fault the condtion codes are unpredictable and the field is left unchanged. The times shown assume all register operands (as is usual for instruction timings). However, if base is changed to a register indexed operand the time is [780-4.00]. All times assume 10 bits extracted starting at bit 4. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*JMP instruction\* .restore .send toc .endif global .index ^Instructions, machine> NEQU 0 then {opcode reserved to Digital fault}; {invalidate per-process translation buffer entries}; {load process general registers from process control block}; {load process map, ASTLVL and PME from PCB}; {save PSL and PC on stack for subsequent REI} .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcodes: 06 LDPCTX Load process context .if manual .s 1 .endif manual Description: The process control block is specified by the internal processor register PCBB (process control block base). The general registers are loaded from the PCB, along with the memory management registers describing the address space. The process entries in the translation buffer are cleared. Execution is switched to the kernel stack. The PC and PSL are moved from the PCB to the stack, suitable for use by a REI instruction. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*LOCC instruction\* .restore .send toc .endif global .index ^Instructions, machine> NEQ 0} then {reserved instruction fault}; dst = PRS[procreg] .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C C. Codes not affected if destination is not replaced. .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcode: DB MFPR Move from processor register .if manual .s 1 .endif manual Description: The specified register is stored in dst. The first operand procreg is a longword that contains the register number. Execution may have register specific side effects. A reserved operand fault can occur if the register does not exist. A reserved instruction fault will occur if MFPR is executed in other than kernel mode. .if manual .send toc .ifnot global .save .flags bold .hl 2 ^*Processor registers\* .restore .send toc .endif global .else manual 3 Processor_registers .endif manual .nf The following table is a summary of the registers accessible in the privileged register space. Each mnemonic can be used to form a symbol by prefixing it with "PR_$__". The number of a register, once assigned, will not change across implementations of the VAX of within an implementation. All unsigned positive number are reserved to Digital, all negative number are reserved for customers. .s 1 The type column indicates whether the register is read-only, write-only, or may be both read and written. The scope column indicates whether the register is maintained on a per-process basis or a per-CPU basis. The init column indicates whether the register is set to some predefined initial value. The dashes mean initialization is optional. .s 1 .if manual .test page 15 .endif manual Register Name Mnemonic Number Type Scope Init ======== ==== ======== ====== ==== ===== ==== Kernel stack pointer KSP 0 R/W PROC --- Executive stack pointer ESP 1 R/W PROC --- Supervisor stack pointer SSP 2 R/W PROC --- User stack pointer USP 3 R/W PROC --- Interrupt stack pointer ISP 4 R/W CPU --- P0 base register P0BR 8 R/W PROC --- P0 length register P0LR 9 R/W PROC --- P1 base register P1BR 10 R/W PROC --- P1 length register P1LR 11 R/W PROC --- System base register SBR 12 R/W CPU --- System length register SLR 13 R/W CPU --- Process control block base PCBB 16 R/W PROC --- System block base SCBB 17 R/W CPU --- Interrupt level IPL 18 R/W CPU yes AST level ASTLVL 19 R/W PROC yes Software interrupt request SIRR 20 W CPU --- Software interrupt summary SISR 21 R/W CPU yes Interval clock control ICCS 24 R/W CPU yes .if manual .test page 12 .endif manual Next interval count NICR 25 W CPU --- Interval count ICR 26 R CPU --- Time of year TODR 27 R/W CPU no Console receiver C/S RXCS 32 R/W CPU yes Console receiver D/B RXDB 33 R CPU --- Console transmit C/S TXCS 34 R/W CPU yes Console transmit D/B TXDB 35 W CPU --- Memory management enable MAPEN 56 R/W CPU yes Trans. buf. inval. all TBIA 57 W CPU --- Trans. buf. inval. single TBIS 58 W CPU --- Performance monitor enable PMR 61 R/W PROC yes System identification SID 62 R CPU no .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*MNEGx instructions\* .restore .send toc .endif global .else manual 2 MNEGx .endif manual .nf Purpose: move the arithmetic negation of a scalar quantity .if manual .s 1 .endif manual Format: opcode src.rx,dst.wx .if manual .s 1 .endif manual Operation: dst = -scr .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0 (floating), V = overflow (integer), C = {dst NEQ 0} (integer), C = 0 (floating) .if manual .s 1 .endif manual Exceptions: Integer overflow, reserved operand (floating) .if manual .s 1 .endif manual Opcodes: 8E MNEGB Move negated byte [780-0.40] .index ^Instructions, machine> NEQ 0} then {reserved instruction fault}; PRS[procreg] = src .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C C. Codes not affected if register is not replaced. .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcode: DA MTPR Move to processor register .if manual .s 1 .endif manual Description: The specified register is loaded. The second operand procreg is a longword that contains the register number. Execution may have register-specific side effects. A reserved operand fault can occur if the register does not exist. A reserved instruction fault will occur if the instruction is executed in other than kernel mode. See the instruction MFPR for a list of processor registers. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*MULxx instructions\* .restore .send toc .endif global .else manual 2 MULxx .endif manual .nf Purpose: perform arithmetic multiplication .if manual .s 1 .endif manual Format: opcode mulr.rx,prod.mx ;2 operand opcode mulr.rx,muld.rx,prod.wx ;3 operand .if manual .s 1 .endif manual Operation: prod = prod * mulr ;2 operand prod = muld * mulr ;3 operand .if manual .s 1 .endif manual C. Codes: N = {prod LSS 0}, Z = {prod EQL 0}, V = {overflow}, C = 0 .if manual .s 1 .endif manual Exceptions: Integer, floating overflow Floating underflow, reserved operand .if manual .s 1 .endif manual Opcodes: 84 MULB2 Multiply byte 2 operand [780-4.00] .index ^Instructions, machine> is set. The mask is scanned from bit 14 to bit 0. Bit 15 is ignored. .if manual .s 1 .endif manual Notes: The time shown assumes R9 only was popped. If R0 only is popped the time is [780-3.20]. If R0 through R9 are popped the time is [780-7.80]. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*PROBEx instructions\* .restore .send toc .endif global .else manual 2 PROBEx .endif manual .nf Purpose: probe accessibility - verify arguments .if manual .s 1 .endif manual Format: opcode mode.rb,len.rw,base.ab .if manual .s 1 .endif manual Operation: probe__mode = MAXU (mode_<1:0_>, PSL _); condition__codes = {{accessibility of base} AND {accessibilty of (base + ZEXT (len) - 1)} using probe__mode} .if manual .s 1 .endif manual C. Codes: N = 0, V = 0, C = 0, Z = {if {accessible} then 0 else 1} .if manual .s 1 .endif manual Execeptions: Translation not valid .if manual .s 1 .endif manual Opcodes: 0C PROBER Probe read accessibility .index ^Instructions, machine> of the mode operand and the previous mode field of the PSL. Note that probing with a mode operand of 0 is equivalent to probing the previous mode. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*PUSHAx instructions\* .restore .send toc .endif global .else manual 2 PUSHAx .endif manual .nf Purpose: push address - calculate address of quantity .if manual .s 1 .endif manual Format: opcode src.ax .if manual .s 1 .endif manual Operation: -(SP) = src .if manual .s 1 .endif manual C. Codes: N = {result LSS 0}, Z = {result EQL 0}, V = 0, C = 0 .if manual .s 1 .endif manual Exceptions: None .if manual .s 1 .endif manual Opcodes: 9F PUSHAB Push address of byte [780-1.20] .index ^Instructions, machine> is set. The mask is scanned from bit 14 to bit 0. Bit 15 is ignored. .if manual .s 1 .endif manual Notes: The time shown assumes R9 only is pushed. If R0 only is pushed the time is [780-3.80]. If R0 through R9 are pushed the time is [780-16.20]. .if manual .s 1 .endif manual Example: PUSHR _#_^M_ ;saves R1, R6 and R7 .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*REI instruction\* .restore .send toc .endif global .index ^Instructions, machine> LSSU PSL_} OR {{tmp2_ EQLU 1} AND {PSL_ EQLU 0}} OR {{tmp2_ EQLU 1} AND {tmp2_ NEQU 0}} OR {{tmp2_ EQLU 1} AND {tmp2_ EQLU 0}} OR {{tmp2_ GRTU 0} AND {tmp2_ NEQU 0}} OR {tmp2_ LSSU tmp2_} OR {tmp2_ GTRU PSL_} OR {tmp2_ NEQU 0} then {reserved operand fault}; if {tmp2_ EQLU 1} AND {{tmp2_ NEQU 0} OR {tmp2_ NEQU 3}} then {reserved operand fault}; if PSL_ EQLU 1 then ISP = SP else PSL___SP = SP; if PSL_ EQLU 1 then tmp2_ = 1; PC = tmp1; PSL = tmp2; if PSL_ EQLU 0 then begin SP = PSL___SP; if PSL_ GEQU ASTLVL then {request interrupt at IPL 2}; end; {check for software interrupts} .if manual .s 1 .endif manual C. Codes: N = {saved PSL_<3_>}, Z = {saved PSL_<2_>}, V = {saved PSL_<1_>}, C = {saved PSL_<0_>} .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcode: 02 REI Return from exception or interrupt .if manual .s 1 .endif manual Description: A longword is popped from the current stack and held in a temporary PC. A second longword is popped and held in a temporary PSL. Validity of the popped PSL is checked. The current stack pointer is saved and a new stack is selected according to the new PSL current__mode and IS fields. The level of the highest privilege AST is checked against the current access mode to see whether a pending AST can be delivered. Execution resumes with the instruction being executed at the time of the exception or interrupt. Any instruction lookahead in the CPU is reinitialized. .if manual .s 1 .endif manual Notes: The exception or interrupt service routine is responsible for restoring any registers saved and removing any parameters from the stack. As usual for faults, any access violation or translation not valid conditions on the stack restore the stack pointer and fault. The noninterrupt stack pointers may be fetched and stored by hardware either in internal registers or in their allocated slots in the Process Control block. MFPR and MTPR always fetch and store the pointers whether in registers or the Process Control Block. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*REMQUE instruction\* .restore .send toc .endif global .index ^Instructions, machine>, Z = tmp1_<2_>, V = tmp1_<1_>, C = tmp1_<0_> .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcode: 04 RET Return from procedure [780-4.60] .if manual .s 1 .endif manual Description: SP is replaced with FP plus 4. A longword containing stack alignment in bits 31:30, a CALLS/CALLG flag in bit 29, the low 12 bits of the procedure entry mask in bits 27:16 and a saved PSW in bits 15:0 is popped from the stack and saved in a temporary (tmp1). PC, FP and AP are replaced by longwords popped from the stack. A register restore mask is formed from bits 27:16 of tmp1. Scanning from bit 0 to bit 11 of tmp1, the contents of the registers whose numbers are indicated by set bits in the restore mask are replaced by longwords popped from the stack. SP is incremented by bits 31:30 of tmp1. PSW is replaced by bits 15:0 of tmp1. If bit 29 of tmp1 is 1 (indicating a CALLS was used) a longword containing the number of arguments is popped from the stack. Four times the unsigned value of the low byte of this longword is added to SP and SP is replaced by the result. .if manual .s 1 .endif manual Notes: A reserved operand fault occurs if tmp1_<15:8_> NEQ 0. The condition codes will be unpredictable if a reserved operand fault occurs. The value of bit 28 of tmp1 is ignored. The time shown is for a return from a CALLS where no registers were saved. The corresponding time for a CALLG return is [780-4.20]. If R0 through R9 are saved the times are CALLS - [780-9.60], CALLG - [780-9.20]. No arguments were passed in the CALLS timing examples. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*ROTL instruction\* .restore .send toc .endif global .index ^Instructions, machine> NEQU 0 then {opcode reserved to Digital fault}; {save process general registers in the process control block}; {remove PSL and PC from stack and save in PCB}; {switch to interrupt stack} .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcodes: 07 SVPCTX Load process context .if manual .s 1 .endif manual Description: The process control block is specified by the internal processor register PCBB (process control block base). The general registers are saved in the PCB. If the current stack in use is the kernel stack, execution is changed to the interrupt stack. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*TSTx instructions\* .restore .send toc .endif global .else manual 2 TSTx .endif manual .nf Purpose: arithmetic compare of a scalar to 0. .if manual .s 1 .endif manual Format: opcode src.rx .if manual .s 1 .endif manual Operation: src - 0 .if manual .s 1 .endif manual C. Codes: N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = 0 .if manual .s 1 .endif manual Exceptions: None (integer), reserved operand (floating) .if manual .s 1 .endif manual Opcodes: 95 TSTB Test byte [780-0.40] .index ^Instructions, machine>